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SyncMOS Technologies International, Inc.
SM59364
8-Bits Micro-controller 64KB ISP flash & 1KB RAM embedded
Product List
SM59364C25, 25MHz 64KB internal flash MCU SM59364C40, 40MHz 64KB internal flash MCU
Features
Working Voltage:4.5V through 5.5V General 8052 family compatible 12 clocks per machine cycle 64K byte on chip program flash with in-System Programming(ISP) capability 1024 bytes on chip data RAM Three 16 bit Timers/Counters One Watch Dog Timer Three 8-bit I/O ports for PLCC package Full duplex serial channel Bit operation instruction Industrial Level 8-bit Unsigned Division 8-bit Unsigned Multiply BCD arithmetic Direct Addressing Indirect Addressing Nested Interrupt Two priority level interrupt A serial I/O port Power save modes: Idle mode and Power down mode Code protection function Low EMI (inhibit ALE) Reset with address $0000 blank initiate ISP service program
Description
The SM59364 series product is an 8 - bit single chip micro controller with 64KB flash & 1K byte RAM embedded. It has In-System Programming (ISP) function and is a derivative of the 8052 micro controller family. With its hardware features and powerful instruction set, it's straight forward to make it a versatile and cost effective controller for those applications which demand up to 24 I/O pins for PLCC package, or applications which need up to 64K byte flash memory either for program or for data or mixed. The on-chip flash memory can be programmed in either parallel or serial interface with its ISP feature.
Ordering Information
yymmv SM59364ihhkL yy: year, mm: month v: version identifier{ , A, B,...} i: process identifier {L=3.0V~3.6V,C=4.5V~ 5.5V} hh: working clock in MHz {25, 40} k: package type postfix {as below table} L:PB Free identifier {No text is Non-PB FreePis PB Free}
Postfix H Package 32L PLCC Pin / Pad Configuration Page 2 Dimension Page 19
Taiwan 6F, No.10-2 Li- Hsin 1st Road , Science-based Industrial Park, Hsinchu, Taiwan 30078 TEL: 886-3-567-1820 886-3-567-1880 FAX: 886-3-567-1891 886-3-567-1894
Specifications subject to change without notice contact your sales representatives for the most recent information.
IDMMX-0033 1
Ver B SM59364 04/2008
SyncMOS Technologies International, Inc.
Pin Configuration
SM59364
8-Bits Micro-controller 64KB ISP flash & 1KB RAM embedded
4 RXD/P3.0 TXD/P3.1 #INT0/P3.2 #INT1/P3.3 T0/P3.4 T1/P3.5 #WE/P3.6 #RD/P3.7 XTAL2 13 14 5
1
30 29 AD5/P0.5 AD6/P0.6 AD7/P0.7 #EA ALE #PSEN A15/P2.7 A14/P2.6 20 21 A13/P2.5
Specifications subject to change without notice contact your sales representatives for the most recent information.
IDMMX-0033 2
Ver B SM59364 04/2008
SyncMOS Technologies International, Inc.
SM59364
8-Bits Micro-controller 64KB ISP flash & 1KB RAM embedded
Block Diagram
Timer 2 Timer 1 Timer 0 Stack Pointer
Decoder & Register 1024 Bytes Ram
Buffer WDT ACC Reset Circuit Power Circuit
To pertinent blocks
DPTR
To whole chip
Buffer2
Buffer1
PC Incrementer
Interrupt Circuit
To pertinent blocks
ALU Timer 2
Xtal2 Xtal1 #EA ALE #PSEN
Timing Generator
To whole system
PSW
Timer 2
Instruction
Register
ISP 64 K Bytes Program Flash
FFFFH
Port 0 Latch
Port 2 Latch
Port 3 Latch
0000H
Port 0 Driver & Mux 8
Port 2 Driver & Mux 8
Port 3 Driver & Mux 8
Specifications subject to change without notice contact your sales representatives for the most recent information.
IDMMX-0033
3
Ver B SM59364 04/2008
SyncMOS Technologies International, Inc.
SM59364
8-Bits Micro-controller 64KB ISP flash & 1KB RAM embedded
Pin Description
32L PLCC Pin#
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3
Symbol
RES P3.0/RXD P3.1/TXD P3.2/#INT0 P3.3/#INT1 P3.4/T0 P3.5/T1 P3.6/#WR P3.7/#RD XTAL2 XTAL1 VSS P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 #PSEN ALE #EA P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VDD
Active
H
I/O
i i/o i/o i/o i/o i/o i/o i/o i/o o i i/o i/o i/o i/o i/o i/o i/o i/o o o I i/o i/o i/o i/o i/o i/o i/o i/o
Names
Reset bit 0 of port 3 & Receiver data bit 1 of port 3 & Transmit data bit 2 of port 3 & low true interrupt 0 bit 3 of port 3 & low true interrupt 1 bit 4 of port 3 & Timer 0 bit 5 of port 3 & Timer 1 bit 6 of port 3 & ext. memory write bit 7 of port 3 & ext. memory read Crystal out Crystal in Sink Voltage, Ground bit 0 of port 2 & bit 8 of ext. memory address bit 1 of port 2 & bit 9 of ext. memory address bit 2 of port 2 & bit 10 of ext. memory address bit 3 of port 2 & bit 11 of ext. memory address bit 4 of port 2 & bit 12 of ext. memory address bit 5 of port 2 & bit 13 of ext. memory address bit 6 of port 2 & bit 14 of ext. memory address bit 7 of port 2 & bit 15 of ext. memory address program storage enable address latch enable external access bit 7 of port 0 & data/address bit 7 of ext. memory bit 6 of port 0 & data/address bit 6 of ext. memory bit 5 of port 0 & data/address bit 5 of ext. memory bit 4 of port 0 & data/address bit 4 of ext. memory bit 3 of port 0 & data/address bit 3 of ext. memory bit 2 of port 0 & data/address bit 2 of ext. memory bit 1 of port 0 & data/address bit 1 of ext. memory bit 0 of port 0 & data/address bit 0 of ext. memory Drive Voltage
L/L/-
L L
Special Function Register (SFR)
The address $80 to $FF can be accessed by direct addressing mode only. Address $80 to $FF is SFR area. The following table lists the SFRs which are identical to general 8052 as well as SM59364 Extension SFRs .
Specifications subject to change without notice contact your sales representatives for the most recent information.
IDMMX-0033
4
Ver B SM59364 04/2008
SyncMOS Technologies International, Inc.
SM59364
8-Bits Micro-controller 64KB ISP flash & 1KB RAM embedded
Special Function Register (SFR) Memory Map
$F8 $F0 $E8 $E0 $D8 $D0 $C8 $C0 $B8 $B0 $A8 $A0 $98 $90 $88 $80 $FF $F7 $EF $E7 $DF $D7 $CF $C7 $BF $B7 $AF $A7 $9F $97 $8F $87
B ACC PSW T2CON IP P3 IE P2 SCON TCON P0
ISPFAH
ISPFAL
ISPFD
ISPC
T2MOD
RCAP2L
RCAP2H
TL2
TH2 SCONF
SBUF TMOD SP TL0 DPL TL1 DPH TH0 TH1 RCON
WDTC
PCON
Note: The text of SFRs with bold type characters are Extension Special Function Registers for SM59364
Addr 85H 9FH BFH C9H D8H F4H F5H F6H F7H SFR RCON WDTC SCONF T2MOD P4 ISPFAH ISPFAL ISPFD ISPC Reset ******00 0*0**000 0****010 ******00 ****1111 00H 00H 00H 0*****00 FA15 FA7 FD7 START FA14 FA6 FD6 FA13 FA5 FD5 FA12 FA4 FD4 WDTE WDR * * * * * P4.3 FA11 FA3 FD3 Reserved** CLEAR PS2 ISPE * P4.2 FA10 FA2 FD2 7 6 5 4 3 2 1 RAMS1 PS1 OME T2OE P4.1 FA9 FA1 FD1 F1 0 RAMS0 PS0 ALEI DCEN P4.0 FA8 FA0 FD0 F0
** Keep to "0" when write WDTC (9FH).
Extension Function Description
1. Memory Structure
The SM59364 is the general 8052 hardware core to integrate the ISP function as a single chip micro controller. It's memory structure follows general 8052 structure .
1.1 Program Memory
The SM59364 has 64K byte on-chip flash memory which used as general program memory, on which include 512 byte specific ISP service program memory space. The address range for the 64K byte is $0000 to $FFFF. The address range for the ISP service program is $FE00 to $FFFF.
Specifications subject to change without notice contact your sales representatives for the most recent information.
IDMMX-0033
5
Ver B SM59364 04/2008
SyncMOS Technologies International, Inc.
SM59364
8-Bits Micro-controller 64KB ISP flash & 1KB RAM embedded
1.1.1 Program Code Security
MOVC instruction executed from external program memory space will not be able to fetch internal codes from on chip program memory after the chip is protected on the Writer.
1.2 Data Memory
The SM59364 has 1K bytes on-chip RAM, 256 bytes of it are the same as general 8052 internal memory structure while the expanded 768 bytes on-chip RAM can be accessed by external memory addressing method (by instruction MOVX.).
1.2.1 Data Memory - Lower 128 byte ($00 to $7F)
Data Memory $00 to $FF is the same as 8052. The address $00 to $7F can be accessed by direct and indirect addressing modes. Address $00 to $1F is register area. Address $20 to $2F is memory bit area. Address $30 to $7F is for general memory area.
Specifications subject to change without notice contact your sales representatives for the most recent information.
IDMMX-0033 6
Ver B SM59364 04/2008
SyncMOS Technologies International, Inc.
1.2.2 Data Memory - Higher 128 byte ($80 to $FF)
The address $80 to $FF can be accessed by indirect addressing mode . Address $80 to $FF is data area.
SM59364
8-Bits Micro-controller 64KB ISP flash & 1KB RAM embedded
1.2.3 Data Memory - Expanded 768 bytes ($0000 to $02FF)
From external address $0000 to $02FF is the on-chip expanded RAM area, total 768 bytes. This area can be accessed by external direct addressing mode (by instruction MOVX). If the address of instruction MOVX @DPTR is larger than $02FF then SM59364 will generate the external memory control signal automatically. The bit 1 (OME) of special function register $BF (SCONF) can enable or disable this expanded 768 byte RAM. The default setting of OME bit is 1 (enable).
System Control Register (SCONF, $BF)
bit-7 WDR Read / Write: Reset value: R/W 0 Unused * Unused * Unused * DFEN * ISPE R/W 0 OME R/W 1 bit-0 ALEI R/W 0
WDR: Watch Dog Timer Reset. When system reset by Watch Dog Timer overflow, WDR will be set to 1. ISPE: ISP function enable bit OME: 768 bytes on-chip RAM enable bit . ALEI: ALE output inhibit bit, to reduce EMI . Setting bit 0 (ALEI) of SCONF can inhibit the clock signal in Fosc/6Hz output to the ALE pin. The bit 1 (OME) of SCONF can enable or disable the on-chip expanded 768 byte RAM. The default setting of OME bit is 1 (enable). The bit 7 (WDR) of SCONF is Watch Dog Timer Reset bit. It will be set to 1 when reset signal generated by WDT overflow. User should check WDR bit whenever un-predicted reset happened.
2. In-System Programming (ISP) Function
The SM59364 can generate flash control signal by internal hardware circuit. User utilize flash control register, flash address register and flash data register to perform the ISP function without removing the SM59364 from the system. The SM59364 provides internal flash control signals which can do flash program/chip erase/page erase/protect functions. User need to design and use any kind of interface which SM59364 can input data. User then utilize ISP service program to perform the flash program/chip erase/page erase/protect functions.
2.1 ISP Service Program
The ISP service program is a user developed firmware program which resides in the ISP service program space. After user developed the ISP service program, user then determine the size of the ISP service program. User need to program the ISP service program in the SM59364 for the ISP purpose. The ISP service program were developed by user so that it should includes any features which relates to the flash memory programming function as well as communication protocol between SM59364 and host device which output data to the SM59364. For example, if user utilize UART interface to receive/transmit data between SM59364 and host
Specifications subject to change without notice contact your sales representatives for the most recent information.
IDMMX-0033 7
Ver B SM59364 04/2008
SyncMOS Technologies International, Inc.
SM59364
8-Bits Micro-controller 64KB ISP flash & 1KB RAM embedded device, the ISP service program should include baud rate, checksum or parity check or any error-checking mechanism to avoid data transmission error. The ISP service program can be initiated under SM59364 active or idle mode. It can not be initiated under power down mode.
2.2 Initiate ISP Service Program
To initiate the ISP service program is to load the program counter (PC) with start address of ISP service program and execute it. There are two ways to do so: (1) Blank reset. Hardware reset with first flash address blank ($0000=#FFH) will load the PC with start address of ISP service program. (2) Execute `JUMP' instruction can load the start address of the ISP service program to PC. User can initiate general 8052 INT function to initiate the ISP service program. After ISP service program executed, user need to reset the SM59364, either by hardware reset or by WDT, or jump to the address $0000 to re-start the firmware program.
ISP Registers - ISPFAH, ISPFAL, ISPFD and ISPC ISP Flash Address-High Register(ISPFAH,$F4)
bit-7 FA15 Read / Write: R/W FA14 R/W FA13 R/W FA12 R/W 0 FA11 R/W 0 FA10 R/W 0 FA9 R/W 0 bit-0 FA8 R/W 0
Reset value: 0 0 0 FA15 ~ FA8: flash address-high for ISP function
ISP Flash Address-Low Register(ISPFAL,$F5)
bit-7 FA7 Read / Write: Reset value: R/W 0 FA6 R/W 0 FA5 R/W 0 FA4 R/W 0 FA3 R/W 0 FA2 R/W 0 FA1 R/W 0 bit-0 FA0 R/W 0
FA7 ~ FA0: flash address-low for ISP function The ISPFAH & ISPFAL provide the 16-bit flash memory address for ISP function. The flash memory address should not include the ISP service program space address. If the flash memory address indicated by ISPFAH & ISPFAL registers overlay with the ISP service program space address, the flash program/page erase of ISP function executed thereafter will have no effect.
Specifications subject to change without notice contact your sales representatives for the most recent information.
IDMMX-0033 8
Ver B SM59364 04/2008
SyncMOS Technologies International, Inc.
ISP Flash Data Register (ISPFD, $F6)
bit-7 FD7 Read / Write: R/W
SM59364
8-Bits Micro-controller 64KB ISP flash & 1KB RAM embedded
FD6 R/W
FD5 R/W 0
FD4 R/W 0
FD3 R/W 0
FD2 R/W 0
FD1 R/W 0
bit-0 FD0 R/W 0
Reset value: 0 0 FD7 ~FD0 : flash data for ISP function
The ISPFD provide the 8-bit data for ISP function
ISP Flash Control Register (ISPC, $F7)
bit-7 START Read / Write: Reset value: R/W 0 bit-0 ISPF0 R/W 0
Unused *
Unused *
Unused *
Unused *
Unused *
ISPF1 R/W 0
F[1: 0]: ISP function select bit START: ISP function start bit = 1: start ISP function which indicated by bit 1, bit 0 (F1, F0) = 0: no operation The START bit is read-only by default, software must write three specific values 55H, AAH and 55H sequentially to the ISPFD register to enable the START bit write attribute. That is: MOV ISPFD, #55H MOV ISPFD, #0AAH MOV ISPFD, #55H Any attempt to set START bit will not be allowed without the procedure above. After START bit set to 1 then the SM59364 hardware circuit will latch address and data bus and hold the program counter until the START bit reset to 0 when ISP function finished. User does not need to check START bit status by software method. F[1:0] 00 01 10 11 ISP function Byte program Chip protect Page erase Chip erase
F[1:0]: ISP function select bit One page of flash memory is 512 byte. To perform byte program/page erase ISP function, user need to specify flash address at first. When performing page erase function, SM59364 will erase entire page which flash address indicated by ISPFAH & ISPFAL registers located within the page. e.g. flash address: $XYMN
Specifications subject to change without notice contact your sales representatives for the most recent information.
IDMMX-0033 9
Ver B SM59364 04/2008
SyncMOS Technologies International, Inc.
SM59364
8-Bits Micro-controller 64KB ISP flash & 1KB RAM embedded page erase function will erase from $XY00 to $X(Y+1)FF (Y:even number), or page erase function will erase from $X(Y-1) 00 to $XYFF (Y:odd number) To perform the chip erase ISP function, SM59364 will erase all the flash program memory except the ISP service program space, also, SM59364 will un-protect the flash memory automatically. To perform chip protect ISP function, the SM59364 flash memory content will be read #00H. e.g. ISP service program to do the byte program - to program #22H to the address $1005H MOV SCONF,#04H MOV ISPFAH,#10H MOV ISPFAL,#05H MOV ISPFD,#22H MOV ISPC,#80H ; enable SM59364 ISP function ; set flash address-high, 10H ; set flash address-low, 05H ; set flash data to be programmed, data = 22H ; start to program #22H to the flash address $1005H ; after byte program finished, START bit of ISPC will be reset to 0 automatically ; program counter then point to the next instruction
ISP Registers - System Control Register (SCONF,$BF)
bit-7 WDR Read / Write: Reset value: R/W 0 Unused * Unused * Unused * Unused * ISPE R/W 0 OME R/W 1 bit-0 ALEI R/W 0
The bit 2 (ISPE) of SCONF is ISP enable bit. User can enable overall SM59364 ISP function by setting ISPE bit to 1, to disable overall ISP function by set ISPE to 0. The function of ISPE behaves like a security key. User can disable overall ISP function to prevent software program be erased accidentally.
3. Watch Dog Timer
The Watch Dog Timer (WDT) is a 16-bit free-running counter that generate reset signal if the counter overflows. The WDT is useful for systems which are susceptible to noise, power glitches, or electronics discharge which causing software dead loop or runaway. The WDT function can help user software recover form abnormal software condition. The WDT is different from Timer0, Timer1 and Timer2 of general 8052. To prevent a WDT reset can be done by software periodically clearing the WDT counter. User should check WDR bit of SCONF register whenever un-predicted reset happened The WDT has selectable divider input for the time base source clock. To select the divider input, the setting of bit2~bit0 (PS2~PS0) of Watch Dog Timer Control Register (WDTC) should be set accordingly. To enable the WDT is done by setting 1 to the bit 7 (WDTE) of WDTC. After WDTE set to 1, the 16-bit counter starts to count with the selected time base source clock which set by PS2~PS0. It will generate a reset signal when overflows. The WDTE bit will be cleared to 0 automatically when SM59364 been reset, either hardware reset or WDT reset. To reset the WDT is done by setting 1 to the CLEAR bit of WDTC. This will clear the content of the 16-bit counter and let the counter re-start to count from the beginning.
Specifications subject to change without notice contact your sales representatives for the most recent information.
IDMMX-0033 10
Ver B SM59364 04/2008
SyncMOS Technologies International, Inc.
SM59364
8-Bits Micro-controller 64KB ISP flash & 1KB RAM embedded
3.1 Watch Dog Timer Registers: WDTC and SCONF Watch Dog Timer Registers - WDT Control Register (WDTC, $9F)
bit-7 WDTE Read / Write: Reset value: R/W reserved** Clear R/W Unused Unused * PS2 R/W 0 PS1 R/W 0 bit-0 PS0 R/W 0
0 * 0 * ** Keep to "0" when write WDTC (9FH).
WDTE : Watch Dog Timer enable bit CLEAR : Watch Dog Timer reset bit PS[2:0] : Overflow period select bits
PS [2:0] 000 001 010 011 100 101 110 111
Divider(OSC in) 8 16 32 64 128 256 512 1024
Time Period (ms) @ 40 MHZ 13.12.048 26.21 52.42 104.8 209.71 419.43 838.86 1677.72
Watch Dog Timer Register - System Control Register (SCONF, $BF)
bit-7 WDR Read / Write: Reset value: R/W 0 Unused * Unused * Unused * Unused * ISPE R/W 0 OME R/W 1 bit-0 ALEI R/W 0
The bit 7 (WDR) of SCONF is Watch Dog Timer Reset bit. It will be set to 1 when reset signal generated by WDT overflow. User should check WDR bit whenever un-predicted reset happened.
Specifications subject to change without notice contact your sales representatives for the most recent information.
IDMMX-0033 11
Ver B SM59364 04/2008
SyncMOS Technologies International, Inc.
SM59364
8-Bits Micro-controller 64KB ISP flash & 1KB RAM embedded
4. Reduce EMI Function
The SM59364 allows user to reduce the EMI emission by setting 1 to the bit 0 (ALEI) of SCONF register. This function will inhibit the clock signal in Fosc/6Hz output to the ALE pin.
Operating Conditions
Symbol TA VCC5 Fosc 25 Fosc 40 Description Operating temperature Supply voltage Oscillator Frequency Oscillator Frequency Min. -40 4.5 3.0 3.0 Typ. 25 5.0 25 40 Max. 85 5.5 25 40 Unit.
Remarks Ambient temperature under bias
V MHz MHz For 5V application For 5V application
DC Characteristics
(TA = -40 degree C to 85 degree C, Vcc = 5.5V) Symbol
VIL1 VIL2 VIH1 VIH2 VOL1 VOL2 VOH1 VOH2 IIL ITL ILI R RES C IO I CC
Parameter
Input Low Voltage Input Low Voltage Input High Voltage Input High Voltage Output Low Voltage Output Low Voltage Output High Voltage Output High Voltage Logical 0 Input Current Logical Transition Current Input Leakage Current Reset Pull-down Resistance Pin Capacitance Power Supply Current
Valid
port 0,2,3,4,#EA RES, XTAL1 port 0,2,3,4,#EA RES, XTAL1 port 0, ALE, #PSEN port 2,3,4 port 0 port 2,3,4,ALE,#PSEN port 2,3,4 port 2,3,4 port 0, #EA RES Vdd
Min. -0.5 0 2.0 70%Vcc
Max. 0.8 0.8 Vcc+0.5 Vcc+0.5 0.45 0.45
Unit V V V V V V V V V V Vcc=5V
Test Conditions
IOL=3.2mA IOL=1.6mA IOH=-800uA IOH=-80uA IOH=-60uA IOH=-10uA Vin=0.45V Vin=2.0V 0.45V2.4 90%Vcc 2.4 90%Vcc -75 -650 10 50 300 10 20 6.5 50
uA uA uA Kohm pF mA mA uA
Freq=1MHz, Ta=25 Active mode, 16MHz Idle mode, 16MHz Power down mode
Note1:Under steady state (non-transient) conditions, IOL must be externally Limited as follows : Maximum IOL per port pin : 10mA Maximum IOL per 8-bit port : port 0 :26mA port 2,3 :15mA Maximum total IOL for all output pins : 71mA If IOL exceeds the condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.
Specifications subject to change without notice contact your sales representatives for the most recent information.
IDMMX-0033 12
Ver B SM59364 04/2008
SyncMOS Technologies International, Inc.
SM59364
8-Bits Micro-controller 64KB ISP flash & 1KB RAM embedded
AC Characteristics
(16/25/40MHz, operating conditions; CL for Port 0, ALE and PSEN Outputs=150pF; CL for all Other Output=80pF) Symbol T LHLL T AVLL T LLAX T LLIV T LLPL T PLPH T PLIV T PXIX T PXIZ T AVIV T PLAZ T RLRH T WLWH T RLDV T RHDX T RHDZ T LLDV T AVDV T LLYL T AVYL T QVWH T QVWX T WHQX T RLAZ T YALH T CHCL T CLCX T CLCH T CHCX Parameter ALE pulse width Address Valid to ALE low Address Hold after ALE low ALE low to Valid Instruction In ALE low to #PSEN low #PSEN pulse width #PSEN low to Valid Instruction In Instruction Hold after #PSEN Instruction Float after #PSEN Address to Valid Instruction In #PSEN low to Address Float #RD pulse width #WR pulse width #RD low to Valid Data In Data Hold after #RD Data Float after #RD ALE low to Valid Data In Address to Valid Data In ALE low to #WR High or #RD low Data Valid to #WR High Data Valid to #WR transition Data hold after #WR #RD low to Address Float #WR or #RD high to ALE high clock fall time clock low time clock rise time clock high time 63 1/fosc Valid Cycle RD/WRT RD/WRT RD/WRT RD RD RD RD RD RD RD RD RD WRT RD RD RD RD RD RD/WRT WRT WRT WRT RD RD/WRT 53 72 T -10 178 230 403 38 73 0 145 590 542 197 3xT-10 4xT-20 7xT-35 T - 25 T + 10 5 T + 10 365 365 302 0 2xT+20 8xT - 10 9xT - 20 3xT+10 0 87 292 10 6xT - 10 6xT - 10 5xT - 10 53 173 177 0 T + 25 5xT -20 10 fosc=16MHz Min. Typ. Max 115 43 53 240 T - 10 3xT - 15 3xT-10 Min. 2xT - 10 T - 20 T - 10 4xT-10 Variable fosc Typ. Max nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS Unit Remarks
Address Valid to #WR or #RD low RD/WRT
T, TCLCL clock period
Specifications subject to change without notice contact your sales representatives for the most recent information.
IDMMX-0033 13
Ver B SM59364 04/2008
SyncMOS Technologies International, Inc.
SM59364
8-Bits Micro-controller 64KB ISP flash & 1KB RAM embedded
ISP Test Conditions
(40 MHZ, typical operating conditions, valid for SM59364 series) Symbol Chip erase Page erase Program Protect MAX 3000ms 10ms 30us 400us Remark Vcc = 5V " " "
Application Reference Valid for SM59364
X'tal C1 C2 R X'tal C1 C2 R 3MHz 30 pF 30 pF open 16MHz 30 pF 30 pF open 6MHz 30 pF 30 pF open 25MHz 15 pF 15 pF 62K 9MHz 30 pF 30 pF open 33MHz 5 pF 5 pF 6.8K 12MHz 30 pF 30 pF open 40MHz 2 pF 2 pF 4.7K
C1
XTAL2
Crystal
SM59364
R C2
XTAL1 VSS
NOTE: Oscillation circuit may differs with different crystal or ceramic resonator in higher oscillation frequency which was due to each crystal or ceramic resonator has its own characteristics. User should check with the crystal or ceramic resonator manufacture for appropriate value of external components.
Specifications subject to change without notice contact your sales representatives for the most recent information.
IDMMX-0033 14
Ver B SM59364 04/2008
SyncMOS Technologies International, Inc.
Data Memory Read Cycle Timing
SM59364
8-Bits Micro-controller 64KB ISP flash & 1KB RAM embedded
Program Memory Read Cycle Timing
Specifications subject to change without notice contact your sales representatives for the most recent information.
IDMMX-0033 15
Ver B SM59364 04/2008
SyncMOS Technologies International, Inc.
Data Memory Write Cycle Timing
SM59364
8-Bits Micro-controller 64KB ISP flash & 1KB RAM embedded
I/O Ports Timing
T6 T7 T8 T9 T10 T11 T12 T1 T2 T3 T4 T5 T6 T7 T8
X1
Sampled
Input P0
Sampled
Input P2,P3
Output by Mov Px,Src RxD at Serial Port Shift Clock (Mode 0)
current data
next data
Sampled
Specifications subject to change without notice contact your sales representatives for the most recent information.
IDMMX-0033 16
Ver B SM59364 04/2008
SyncMOS Technologies International, Inc.
Timing Critical, Requirement of External Clock (Vss=0.0V is assumed)
SM59364
8-Bits Micro-controller 64KB ISP flash & 1KB RAM embedded
Tm.I External Program Memory Read Cycle
Tm.II External Data Memory Read Cycle
Specifications subject to change without notice contact your sales representatives for the most recent information.
IDMMX-0033 17
Ver B SM59364 04/2008
SyncMOS Technologies International, Inc.
Tm.III External Data Memory Write Cycle
SM59364
8-Bits Micro-controller 64KB ISP flash & 1KB RAM embedded
Specifications subject to change without notice contact your sales representatives for the most recent information.
IDMMX-0033 18
Ver B SM59364 04/2008
SyncMOS Technologies International, Inc.
SM59364
8-Bits Micro-controller 64KB ISP flash & 1KB RAM embedded
PLCC 32L Package Information
Specifications subject to change without notice contact your sales representatives for the most recent information.
IDMMX-0033 19
Ver B SM59364 04/2008

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